ARC-V Processors Overview

The Synopsys ARC-V™ processors leverage the proven microarchitecture of the existing ARC processor offerings, while giving customers access to the expanding RISC-V ecosystem. The Synopsys ARC-V portfolio, based on the RISC-V ISA, includes high-performance, mid-range, and ultra-low power families, as well as functional safety (FS) versions, to address a broad range of application workloads.

New Generation of RISC-V Synopsys ARC Processors

ARC-V RMX-100 and RMX-500 Series

The 32-bit ARC-V RMX series includes the three-stage-pipeline RMX-100 and the five-stage-pipeline RMX-500 processors, which are optimized for ultra-low power embedded applications. The processors offer optional DSP support for greater signal processing efficiency. The RMX-100 processor offers support for ISO 26262 functional-safety compliance (QM and ASIL-D), and the RMX-500 processor offers support for functional-safety compliance (QM, ASIL-D, ASIL-B, and hybrid mode), as well as ISO 21434 cybersecurity compliance.

More information is available on the Synopsys website:

• Power-Efficient RISC-V Processors for Embedded Applications

• Synopsys ARC-V RMX-100 Processor IP

• Synopsys ARC-V RMX-500 Processor IP

ARC-V RHX Series

The 32-bit ARC-V RHX-100 series consists of superscalar, single-core and multicore processors optimized for efficient real-time applications. It includes support for coherent accelerators and real-time hardware virtualization as well as optional RVV extensions (RHX-100V/105V). For safety-critical applications, the RHX-100 series offers functional-safety-compliant versions of all the processors in the series.

More information is available on the Synopsys website:

• Maximum Performance Efficiency for Real-time Applications

• Synopsys ARC-V RHX-100 Processor IP

ARC-V RPX Processors

The 64-bit ARC-V RPX-100 series consists of multicore processors with 64-bit RISC-V defined profile support for both user and supervisor modes. The multicore ARC-V RPX-105 supports SMP Linux and shared L3 cache. It offers configurations up to 16 cores and is optimized for efficient host processing performance for a variety of applications. The RPX-100 series also offers functional-safety- compliant versions of its processors.

More information is available on the Synopsys website:

• Maximum Performance Efficiency for Host Applications

• ARC-V RPX-100 Procssor IP

Additional Information

Below are some additional resources related to ARC-V processors:

• Announcement of ARC-V Processors portfolio during RISC-V Summit North America 2023: RISC-V: Unleashing the Next Phase of SoC Innovation. John Koeter, SVP of Product Management at Synopsys, explores how Synopsys is enabling new RISC-V technologies to drive the next steps of semiconductor innovation in the automotive, AIoT, HPC, and mobile markets.

RISC-V Standard Conformance

ARC-V processors are based on the RISC-V ISA, and thanks to that allow use of a huge ecosystem of available tools and software. To be compatible with those tools and software requires compliance with base specifications such as the following:

• The RISC-V Instruction Set Manual Volume I: Unprivileged ISA, version 20191213

• The RISC-V Instruction Set Manual Volume II: Privileged Architecture, version 1.12

• RISC-V psABI Specification, version 1.0

• RISC-V Advanced Interrupt Architecture, version 1.0

• RISC-V Semihosting, version 0.2