MWDT vs. GCC option matrix

Option

ARChitect

CCAC

GCC

MDB

Supported core

Notes

Processor Family

ARC600

-a6

-mcpu=arc600

-a6

ARC600

ARC700

-a7

-mcpu=arc700

-a7

ARC700

ARCv2EM

-av2em

-mcpu=arcem

-av2em

ARC EM

ARCv2HS

-av2hs

-mcpu=archs

-av2hs

ARC HS

ARC600 Core Versions

Version 1

-core1

N.A.

-core1

ARC600

Initial version

Version 2

-core2

N.A.

-core2

ARC600

Zeroed BCR Region 0xc0

Version 3

-core3

N.A.

-core3

ARC600

LD/ST Queue changes

Version 4

-core4

N.A.

-core4

ARC600

SYNC instruction

Version 5

-core5

N.A.

-core5

ARC600

ARC600_BUILD BCR

Version 6

-core6

N.A.

-core6

ARC600

Misaligned LD/ST traps.

ARC700 Core Versions

Version 1

-core1

N.A.

-core1

ARC700

Initial version

Version 2

-core2

N.A.

-core2

ARC700

Zeroed BCR Region 0xc0

Version 3

-core3

N.A.

-core3

ARC700

MXP Debug Architecture

Version 4

-core4

N.A.

-core4

ARC700

SWAPE, LLOCK,SCOND instr

ARC EM Core Versions

Version 0

-core0

Not supported

-core0

ARC EM

EM 1.0 (Initial version)

Version 1

-core1

N.A.

-core1

ARC EM

EM 1.1 (Default version)

ARC HS Core Versions

Version 0

-core0

Not supported

-core0

ARC HS

HS 1.0 (Initial version)

Version 1

-core1

N.A.

Shift ISA Extension (shift_option)

Option 1

-Xsa

N.A.

-Xsa (-Xshift_assist)

Option 2

-Xbs

N.A.

-Xbs (-Xbarrel_shifter)

Option 3

-Xsa

-mbarrel-shifter

-Xsa -Xbs

All

Default ON

Code Density Extension

code_density_option

-Xcd

-mcode-density

-Xcd (-Xcode_density )

ARC EM, ARC HS

Default for HS, EM

Bitscan ISA Extension

bitscan_option

-Xnorm

-mnorm

-Xnorm

All

Default for HS

SWAP ISA Extension

swap_option

-Xswap

-mswap

-Xswap

All

Default for HS

DIV_REM ISA option

div_rem_option

-Xdiv_rem

-mdiv-rem

-Xdiv_rem

ARC EM, ARC HS

radix2 is default for EM and HS

Multiply ISA Option (mpy_option)

wlh1

-Xmpy16

-mmpy-option=16

-Xmpy16

ARC600, ARC EM

wlh2

-Xmpy

-mmpy-option=2

-Xmpy

except ARC HS

-Xmpy16 is implied

wlh1, wlh2, wlh3, wlh

-Xmpy_cycles= 1,2,3,4,5

-mmpy-option={3-6}

-Xmpy_cycles=1,2,3,4,5

ARC700, ARC EM

-Xmpy is implied if spec

wlh7

-Xmac

-mmpy-option=7

ARC HS

-Xmac implies -Xmpy and

wlh8

-Xmacd

-mmpy-option=8

ARC HS

-Xmacd implies -Xmac

wlh9

-Xqmpyh

-mmpy-option=9

ARC HS

-Xqmpyh implies -Xmacd

A600 MPY

-Xmult32

-Xmult32

ARC600

A600 MPY cycles

-Xmult32_cycles=N

-mulcost={1,2,3,4,5}

-Xmult32_cycles=N

ARC600

-Xmult32 is implied

64-bit Load and Store

ll64

-Xll64

-mll64

-Xll64

ARC HS

LDD/STD

Unaligned Memory access

-XUnaligned

N.A.

-XUnaligned

ARC HS

Unaligned memory accesses

Atomic Option

atomic_option

-Xatomic

-matomic

-Xatomic

Default

Extended Arithmetic Instructions

-Xea

-mEA

-Xea

ARC600, ARC700

Xlib MetaWare Opt

-Xlib

N.A

-Xlib

ARC600

Expansion: -Xmult32 -Xno

-Xlib

N.A

-Xlib

ARC601

Expansion: -Xbs -Xmult32

-Xlib

N.A.

-Xlib

ARC700

Expansion: -Xmpy (-Xnorm

-Xlib

N.A.

-Xlib

ARC EM

Expansion: -Xbs -Xmpy -X

-Xlib

N.A.

-Xlib

ARC HS

Expansion: -Xmpy -Xll64

Endianness

Big

-HB

-mbig-endian

N/A

MDB reads endianess from ELF

Little

-HL

-mlittle-endian

N/A

PC Width

pc_size

-Hpc_width= 16,20,24,28,

N.A.

-pc_width=16,20,24,28,32

except ARC HS

For HS, fixed pc_width=32

Loop Counter Width

lpc_size

-Hlpc_width= 0,8,12,16,2

N.A.

-lpc_width=8,12,16,20,24

except ARC HS

For HS, fixed lpc_width=32

Address size

addr_size

N/A

N.A.

-addr_size=16,20,24,32

ARC EM

For HS, fixed addr_size=32

Number of Interrupts

number_of_interrupts

N/A

N.A.

-interrupts=1..240

All

For 600,700 only 8,16,24

Interrupt Vector Base

invbase_preset

N/A

N.A.

-interrupt_base=addr

All

Fast Interrupts

irq_option

N/A

N.A.

-firq

ARC EM, ARC HS

External Interrupts

external_interrupts

N/A

N.A.

-ext_interrupts=1..240

ARC EM, ARC HS

Number of priority level

number_of_levels

N/A

N.A.

-interrupt_priorities=1..16

ARC EM, ARC HS

Number of Registers (ngr_num_regs)

16

N.A.

N/A

all

MDB reads -rf16 info fro

32

Default

Default

N/A

all

CCAC assumes 32 registers

Number of Register Bank

ngf_num_banks

N.A.

-rgf_num_banks=1,2,3,4

ARC EM, ARC HS

EM - 2 register banks, H

Number of banked registers

ngf_banked_regs

-Hrgf_banked_regs=N

N.A.

-rgf_banked_regs=4,8,16,32

ARC EM

For HS it is 32 (or 16 w

Actionpoints

num_actionpoints

Timer 0

-Xtimer0

N.A.

-Xtimer0

All

Timer 1

-Xtimer1

N.A.

-Xtimer1

All

DCCM Size

dccm_size

N/A

N.A.

-dccm_size=size

All

User linker map file to

DCCM Base Address

dccm_base

N/A

N.A.

-dccm_base=addr

All

ICCM Size

iccm0_size

N/A

N.A.

-iccm_size=size

All

iccm1_size

-iccm1_size=size

ICCM Base Address

iccm0_base

N/A

N.A.

-iccm_base=addr, -iccm0_X

All

iccm1_base

-iccm1_base=addr

All

Data Cache

dc_size, dc_bsize,

c_ways,

N/A

-param l1-cache-size -param l1-cache-line-size N.A.

-dcache=csz,lsz,w,attrib csz is 512 to 32k lsz is 8,16,32,64,128,256 w is 1,2,4 attrib is a or o

All

csz=cache size, lsz=line size, w=ways, attrib is optional,random

Instruction Cache

ic_size ic_bsize ic_ways

N/A

N.A.

-icache=csz,lsz,w,attrib csz is 512 to 32k lsz is 8,16,32,64,128,256 w is 1,2,4 attrib is a or o

All

Same format as -dcache csz=cache size, lsz=line size, w=ways, attrib is optional,random

Instruction Fetch Queue

ifqueue_size

ARC EM, ARC HS

ifqueue_burst_size

ARC EM, ARC HS

DSP Dual 16x16 MAC

-Xxmac_d16

-Xxmac_d16

ARC600, ARC700

Adds instructions MULDW,

DSP 24x24 MAC

-Xxmac_24

-Xxmac_24

ARC600, ARC700

Adds instructions MULT,

DSP 32x16 MPY

-Xmul32x16

-mmul32x16

-Xmul32x16

ARC600, ARC700

Adds Instructions MULULW

DSP Dual Floating Point

32x16 MUL/MAC

-Xdmulpf

-Xdmulpf

ARC 600

Adds instructions DMULPF

DSP XY memory

-Xxy

-mxy

-Xxy

ARC600, ARC700

XY size

-Xxysize=size

N.A.

-Xxysize=size

ARC600, ARC700

XY banks

-Xxybanks=banks

N.A.

-Xxybanks=banks

ARC600, ARC700

XY base X

-Xxylsbasex=addr

N.A.

-Xxylsbasex=addr

ARC600, ARC700

XY base Y

-Xxylsbasey=addr

N.A.

-Xxylsbasey=addr

ARC600, ARC700

FPX (floating pt.)

Single

-Xspfp

-mspfp

-Xspfp

except ARC HS

Also -Xspfp_compact, -Xs

Double

-Xdpfp

-mdpfp

-Xdpfp

except ARC HS

Also -Xdpfp_compact, -Xd

eFPX (new fp unit)

ARC HS

No support in compiler/d

SIMD Unit

-Xsimd

-msimd

-Xsimd

ARC700

Time Stamp Counter

-Xrtsc

N.A.

-Xrtsc

ARC700

RTSC instruction

Stack Boundary Check

N/A

N.A.

-Xstack_check

ARC700

Memory Management Unit

Version 2

N/A

N.A.

-mmu

ARC700

Version3

N/A

N.A.

-mmuv3 -prop=mmu_pagesize=NNN -prop=jtlb_ways=WWW -prop=mmu_osm=N

ARC700 ARC700 ARC700 ARC700

Provides more configurab Set the page size in byt change the number of way Set the OSM bit, N=1 or

FPU (IEEE fp)

Sngl

-mfpu=fpus

ARC EM, ARC HS

Sngl with DIV/SQRT

-mfpu=fpus_dis

ARC EM, ARC HS

Sngl with fused ops

-mfpu=fpus_fma

ARC EM, ARC HS

Sngl all extensions

-mfpu=fpus_all

ARC EM, ARC HS

Dbl

-mfpu=fpud

ARC HS

Dbl with DIV/SQRT

-mfpu=fpud_dis

ARC HS

Dbl with fused ops

-mfpu=fpud_fma

ARC HS

Dbl all extensions

-mfpu=fpud_all

ARC HS

Dbl assist insns

-mfpu=fpuda

ARC EM